Acer Aspire X1300 Technical Information PDF herunterladen (Seite 27)

Chapter 2 19

DRAM Configuration

Parameter Description Option

Timing Mode When set to auto mode, the system reads the electronic data sheet of the

memory modules and adjusts the timings accordingly.

When set to MaxMemClk, you can manually specify the memory clock

frequency independent of the system bus frequency.

Auto

MaxMemClk

Memory Clock value or Limit Displays the current memory clock frequency.

CKE base power down

mode

All synchronous memory devices can go into sleep mode as soon as the

clock enable (CKE) signal is disasserted. In that case, the internal clocks are

disabled and the memory chip goes into auto-refresh mode which is the

lowest power state at which the memory retains data.

If then power is turned off, the device will lose all data, however, as long as

standby power is maintained, no data loss will occur.

Disabled

Enabled

CKE based power down Sets the CKE power saving through disasserting clock enable using system

level or per channel basis.

Per Channel

Per CS

Memclock tri-stating Enables or disables the memory clock tri-stating during C3 an Alt VD

feature.

Disabled

Memclock tri-

stating during

C3 and Alt VD

Memory Hole Remapping Enables or disables memory remapping around the memory hole. Enabled

Disabled

Auto Optimize Bottom IO Allows you to auto optimize maximal memory size when kernel assigns PCI

Resources.

Enabled

Disabled

Bottom of UMA DRAM

[31:24] [FC]

Allows you to enter a HEX number ranging from 0000 to 00F0. Minimim 0000

Maximum 00FC

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Acer Aspire X1300 Technical Information Seite 27