9
Acer AN1600 F1 Network Storage System Specifications
The primary I/O bus for the main board is PCIe Gen2. The following table lists the characteristics
of the PCI-E bus segments.
PCI express Bus Segment Characteristics of PCI Express Topology
NOTE:
1. "Bus Width" refers to the number of physical electrical lanes running to a PCIe® connector.
2. Default bus assignment (in decimal). Inserting cards with PCI™ bridges may alter the actual bus assignment
number.
3. Slots are enumerated differently based on the operating system. Microsoft® operating systems enumerate Device
ID by bus starting from the lowest bus to the highest.
Embedded dual-port
Gigabit server
adapter (Intel
82576EB) two port
total
10Base-T
100Base-TX
1000Base-TX
IEEE 802.3 10Base-T
IEEE 802.3ab 1000Base-T
IEEE 802.3u 100Base-TX
Four lane (x4), 100 MHz PCI Express reference clock
1000Base-TX (half- and full-duplex)
Virtualization
acceleration
Intel I/O Acceleration Technology
Virtual Machine Device Queues (VMDq)
PCI-SIG SR-IOV implementation
NC-SI SMBus, PXE, iSCSI boot
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