Acer EL1800 Technical Information PDF herunterladen (Seite 53)

Checkpoint Description

Before D0

If boot block debugger is enabled, CPU cache-as-RAM functionality is enabled at this

point. Stack will be enabled from this point.

Early Boot Strap Processor (BSP) initialization like microcode update, frequency and

other CPU critical initialization. Early chipset initialization is done.

Early super I/O initialization is done including RTC and keyboard controller. Serial port

is enabled at this point if needed for debugging. NMI is disabled. Perform keyboard

controller BAT test. Save power-on CPUID value in scratch CMOS. Go to flat mode

with 4GB limit and GA20 enabled.

D2 Verify the boot block checksum. System will hang here if checksum is bad.

Disable CACHE before memory detection. Execute full memory sizing module. If

memory sizing module not executed, start memory refresh and do memory sizing in

Boot block code. Do additional chipset initialization. Re-enable CACHE. Verify that flat

mode is enabled.

Test base 512KB memory. Adjust policies and cache first 8MB. Set stack.

Bootblock code is copied from ROM to lower system memory and control is given to it.

BIOS now executes out of RAM. Copies compressed boot block code to memory in

right segments. Copies BIOS from ROM to RAM for faster access. Performs main

BIOS checksum and updates recovery status accordingly.

Both key sequence and OEM specific method is checked to determine if BIOS

recovery is forced. If BIOS recovery is necessary, control flows to checkpoint E0. See

Bootblock Recovery Code Checkpoints section of document for more information.

Restore CPUID value back into register. The Bootblock-Runtime interface module is

moved to system memory and control is given to it. Determine whether to execute

serial flash.

The Runtime module is uncompressed into memory. CPUID information is stored in

memory.

Store the Uncompressed pointer for future use in PMM. Copying Main BIOS into

memory. Leaves all RAM below 1MB Read-Write including E000 and F000 shadow

areas but closing SMRAM.

Restore CPUID value back into register. Give control to BIOS POST

(ExecutePOSTKernel). See POST Code Checkpoints section of document for more

information.

System is waking from ACPI S3 state

E1-E8

EC-EE

OEM memory detection/configuration error. This range is reserved for chipset vendors

& system manufacturers. The error associated with this value may be different from

one platform to the next.

Initialize the floppy controller in the super I/O. Some interrupt vectors are initialized.

DMA controller is initialized. 8259 interrupt controller is initialized. L1 cache is enabled.

Set up floppy controller and data. Attempt to read from floppy.

Enable ATAPI hardware. Attempt to read from ARMD and ATAPI CDROM.

Disable ATAPI hardware. Jump back to checkpoint E9.

Read error occurred on media. Jump back to checkpoint EB.

Search for pre-defined recovery file name in root directory.

Recovery file not found.

Start reading FAT table and analyze FAT to find the clusters occupied by the recovery

file.

Start reading the recovery file cluster by cluster.

Disable L1 cache.

Check the validity of the recovery file configuration to the current configuration of the

flash part.

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